Among the most important aspects in integrated chip system design are the interface considerations for very short channel Complementary Metal-Oxide-Semiconductor (CMOS) or Bi-polar CMOS (BICMOS) devices, or other very large scale integrated circuit (VLSI) or (ULSI) chips, in high speed applications. Beginning with the driving circuit, an on-chip voltage swing of ground to Vdd (internal power supply) must be communicated off-chip to external devices. The path from the driver output to the output pad involves capacitive coupling effects to other on-chip signals. Moreover, the chip packaging system adds inductances to the circuit. The external signals must then traverse some interconnect (or transmission line), such as card traces or multi-chip module (MCM) connections. The signals are subject to additional deformations at this point due to transmission line effects.
The use of external decoupling capacitors to stabilize the card power supply provided to the chip is known in the art. For low-impedance card power plane connections, these external capacitors do not reduce the on-chip simultaneous switching noise of the driver circuit. Such on-chip simultaneous switching noise can lead to an impedance mis-match between the driving circuit and the card interconnect or transmission line.
Transmission line effects become significant when the round trip propagation delay from the sending chip to the receiving chip is greater than the rise time of the transmitted signal. This condition is almost always met for modern CMOS-based digital systems. When this is the case, reflections occur on the signal line due to impedance mismatches between the source, the transmission line, and the load. These reflections are superimposed on the transmitted signal, causing significant overshoot, undershoot, and system-wide noise. This can cause both performance problems and reliability problems.
The performance problem is a reduction in the valid-data window of transmitted pulses with respect to the system clock. The reliability problem involves devices with ultra-thin gate dielectric layers, less than 5 nm thickness, for which overshoots and undershoots can have a very significant effect in reducing the useful life of the thin gate dielectric. This problem can lead to catastrophic breakdown, causing a serious system reliability problem. The voltage overshoots and undershoots can also cause latch-up in CMOS devices leading to serious reliability problems. For very high speed CMOS applications where the data rates are in the range of 1 GHz to 10 GHz and above, these performance and reliability problems can cause severe design limitations and prove very costly.
The deficiencies of the conventional impedance matching systems show that a need still exists for improvement. To overcome the shortcomings of the conventional systems, a new system and structure for impedance matching in very high speed I/O chip interfacing is provided. It is an object of the present invention to provide a system and device to achieve impedance matching at a driver circuit output, thereby preventing and not merely compensating for high voltage transients (overshoots) and low voltage transients (undershoots). It is another object of the present invention to provide a system and device for impedance matching which can be manufactured on the same chip as the driver circuit. It is yet another object of the present invention to provide a system and device capable of automatically adjusting to provide impedance matching at a driver circuit when operating conditions cause changes to the system. Still another object of the present invention is to provide an impedance matching system capable of performing its functions under a wide range of values for the various components comprising both the on-chip driver circuit and the off-chip interface circuitry.